Referring to FIG. 1, a digital phase locked loop (PLL) produces recovered data or clock signals related in frequency to an input reference signal. A digital phase comparator is generally utilized in conjunction with a charge pump circuit to provide a pulsed error signal indicative of the phase difference between the reference signal and a recovered signal. The charge supplied by the error signal is used to develop a control voltage across a capacitor included within a loop filter. A voltage-controlled oscillator (VCO) operates to vary the frequency of the recovered signal in accordance with the control voltage.
Since the control voltage is required to be both increased and decreased during operation of the VCO, the charge pump circuit typically includes pump up and pump down current generators for supplying positive and negative current pulses, respectively, to the loop filter capacitor. A positive current pulse is synthesized by energizing the pump up generator for an interval longer than that over which the pump down generator is actuated, while a negative pulse is created in the opposite manner. Hence, if the pump up and pump down generators have equivalent magnitudes and rise times a net current of zero will be delivered by the charge pump to the loop filter when the pump generators are contemporaneously activated for identical time intervals.
Unfortunately, the pump up and pump down current generators used in charge pump circuits often have different rise times and/or current magnitudes. For instance, on-chip processing variations may cause the devices within pump circuits of similar architecture to differ in magnitude. Consequently, the net current provided to the loop filter will be zero when the pump up and pump down generators are activated by the phase detector for pulse periods of unequal duration. Since the phase detector actuates one pump generator longer than the other upon determining the phase of the reference and recovered waveforms to be out of alignment, the PLL will become stabilized (i.e. will produce zero charge pump current) with the reference and recovered signals out of phase. Even under the condition of precise frequency lock steady-state phase errors as small as two three nanoseconds can lead to sampling discrepancies at relatively low (e.g. 20 MHz) clock rates.
It is therefore an object of the present invention to provide a phase-locked loop with precisely matched charge pump generators such that subnanosecond phase accuracy may be achieved.